`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/09/19 20:37:31
// Design Name: 
// Module Name: decode
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

/* 把串口传来的指令转变为sw和btn的电平信号 */

module decode(
    input clk,
    input [7:0] code,
    input dc_en,    // 解码使能信号，当为高电平时，所传入的指令数据 code 有效

    output reg [23:0] sw,
    output reg [4:0] btn,
    output reg [23:0] led,      // 可以通过串口直接更改led以及数码管的电平，以便测试采样
    output reg [7:0] bit_sel,
    output reg [7:0] seg_sel,
    output reg turn_start
    );

    always @ (posedge clk) begin
        if (dc_en) begin
            case (code[6:0]) 
                7'd0: sw <= {sw[23:1], code[7]};
                7'd1: sw <= {sw[23:2], code[7], sw[0]};
                7'd2: sw <= {sw[23:3], code[7], sw[1:0]};
                7'd3: sw <= {sw[23:4], code[7], sw[2:0]};
                7'd4: sw <= {sw[23:5], code[7], sw[3:0]};
                7'd5: sw <= {sw[23:6], code[7], sw[4:0]};
                7'd6: sw <= {sw[23:7], code[7], sw[5:0]};
                7'd7: sw <= {sw[23:8], code[7], sw[6:0]};
                7'd8: sw <= {sw[23:9], code[7], sw[7:0]};
                7'd9: sw <= {sw[23:10], code[7], sw[8:0]};
                7'd10: sw <= {sw[23:11], code[7], sw[9:0]};
                7'd11: sw <= {sw[23:12], code[7], sw[10:0]};
                7'd12: sw <= {sw[23:13], code[7], sw[11:0]};
                7'd13: sw <= {sw[23:14], code[7], sw[12:0]};
                7'd14: sw <= {sw[23:15], code[7], sw[13:0]};
                7'd15: sw <= {sw[23:16], code[7], sw[14:0]};
                7'd16: sw <= {sw[23:17], code[7], sw[15:0]};
                7'd17: sw <= {sw[23:18], code[7], sw[16:0]};
                7'd18: sw <= {sw[23:19], code[7], sw[17:0]};
                7'd19: sw <= {sw[23:20], code[7], sw[18:0]};
                7'd20: sw <= {sw[23:21], code[7], sw[19:0]};
                7'd21: sw <= {sw[23:22], code[7], sw[20:0]};
                7'd22: sw <= {sw[23], code[7], sw[21:0]};
                7'd23: sw <= {code[7], sw[22:0]};
                default: sw <= sw;
            endcase
        end
        else 
            sw <= sw;
    end

    always @ (posedge clk) begin
        if (dc_en) begin
            case (code[6:0]) 
                7'd24: btn <= {btn[4:1], code[7]};
                7'd25: btn <= {btn[4:2], code[7], btn[0]};
                7'd26: btn <= {btn[4:3], code[7], btn[1:0]};
                7'd27: btn <= {btn[4], code[7], btn[2:0]};
                7'd28: btn <= {code[7], btn[3:0]};
                default: btn <= btn;
            endcase
        end  
        else
            btn <= btn;
    end

    always @(posedge clk) begin
        if (dc_en) begin
            case (code[6:0]) 
                7'd29: turn_start <= 1'b1;
                default: turn_start <= 1'b0;
            endcase
        end
        else turn_start <= 1'b0;
    end

    /* 用于测试 */
    always @ (posedge clk) begin
        if (dc_en) begin
            case (code[6:0])
                7'd30: led <= {led[23:1], code[7]};
                7'd31: led <= {led[23:2], code[7], led[0]};
                7'd32: led <= {led[23:3], code[7], led[1:0]};
                7'd33: led <= {led[23:4], code[7], led[2:0]};
                7'd34: led <= {led[23:5], code[7], led[3:0]};
                7'd35: led <= {led[23:6], code[7], led[4:0]};
                7'd36: led <= {led[23:7], code[7], led[5:0]};
                7'd37: led <= {led[23:8], code[7], led[6:0]};
                7'd38: led <= {led[23:9], code[7], led[7:0]};
                7'd39: led <= {led[23:10], code[7], led[8:0]};
                7'd40: led <= {led[23:11], code[7], led[9:0]};
                7'd41: led <= {led[23:12], code[7], led[10:0]};
                7'd42: led <= {led[23:13], code[7], led[11:0]};
                7'd43: led <= {led[23:14], code[7], led[12:0]};
                7'd44: led <= {led[23:15], code[7], led[13:0]};
                7'd45: led <= {led[23:16], code[7], led[14:0]};
                7'd46: led <= {led[23:17], code[7], led[15:0]};
                7'd47: led <= {led[23:18], code[7], led[16:0]};
                7'd48: led <= {led[23:19], code[7], led[17:0]};
                7'd49: led <= {led[23:20], code[7], led[18:0]};
                7'd50: led <= {led[23:21], code[7], led[19:0]};
                7'd51: led <= {led[23:22], code[7], led[20:0]};
                7'd52: led <= {led[23], code[7], led[21:0]};
                7'd53: led <= {code[7], led[22:0]};
                default: led <= led;
            endcase 
        end
        else 
            led <= led;
    end
    
    always @ (posedge clk) begin
        if (dc_en) begin
            case(code[6:0]) 
                7'd54: bit_sel <= {bit_sel[7:1], code[7]};
                7'd55: bit_sel <= {bit_sel[7:2], code[7], bit_sel[0]};
                7'd56: bit_sel <= {bit_sel[7:3], code[7], bit_sel[1:0]};
                7'd57: bit_sel <= {bit_sel[7:4], code[7], bit_sel[2:0]};
                7'd58: bit_sel <= {bit_sel[7:5], code[7], bit_sel[3:0]};
                7'd59: bit_sel <= {bit_sel[7:6], code[7], bit_sel[4:0]};
                7'd60: bit_sel <= {bit_sel[7], code[7], bit_sel[5:0]};
                7'd61: bit_sel <= {code[7], bit_sel[6:0]};
            endcase 
        end
    end

    always @ (posedge clk) begin
        if (dc_en) begin
            case(code[6:0]) 
                7'd62: seg_sel <= {seg_sel[7:1], code[7]};
                7'd63: seg_sel <= {seg_sel[7:2], code[7], seg_sel[0]};
                7'd64: seg_sel <= {seg_sel[7:3], code[7], seg_sel[1:0]};
                7'd65: seg_sel <= {seg_sel[7:4], code[7], seg_sel[2:0]};
                7'd66: seg_sel <= {seg_sel[7:5], code[7], seg_sel[3:0]};
                7'd67: seg_sel <= {seg_sel[7:6], code[7], seg_sel[4:0]};
                7'd68: seg_sel <= {seg_sel[7], code[7], seg_sel[5:0]};
                7'd69: seg_sel <= {code[7], seg_sel[6:0]};
            endcase 
        end
    end


    
endmodule
